Computing devices require memory. The memory can include read only memory (ROM) or random access memory (RAM). Generally, memory includes memory cells that are arranged in rows and columns. The individual memory cells are accessed through the use of row select lines and column select lines, typically referred to as word lines and bit lines.
Typically, sense amplifiers are connected to the bit lines for sensing a state of memory cells connected to the bit lines. The sense amplifiers generally each include a differential amplifier. FIG. 1 shows a differential amplifier 100 and an associated current source 130.
The typical differential amplifier of FIG. 1 includes four transistors 110, 112, 114, 116. Input transistors 110, 112 receive differential voltage inputs (VIN+, VIN−). An output (VOUT) is generated across an output transistor 114. The differential amplifier conducts current through a common source node 120.
Generally, the current source 130 is connected to the common source node 120 to provide the differential amplifier with a proper bias current. The current source 130 can include a current mirror. A first transistor 132 mirrors current flowing through a second transistor 134. A current source 136 determines the current flowing through the second transistor 134, and therefore, the current flowing through the first transistor 132, and therefore, the current flowing through the common source node 120. As a result, the current source 136 (ISOURCE) sets the bias current of the differential amplifier 100.
The current source 130 and the differential amplifier implementation shown in FIG. 1 include P-channel transistors. An analogous N-channel current source and differential amplifier implementation is also possible.
A liability of the current source 130, differential amplifier combination of FIG. 1, is that variations of the power supply VDD tend to cause variations of a voltage potential of the common source node 120. The bias current provided by the current source 130 can vary as the power supply voltage VDD varies. The current variance of the current source 130 causes the voltage potential of the common source node 120 to vary. Variations of the voltage potential of the common source node 120 tend to cause voltage variations of the output (VOUT). The net result is that the output (VOUT) is sensitive to variations of the power supply voltage VDD.
The previously mentioned MRAM sense amplifiers require a minimization of power supply sensitivity. MRAM circuitry selects and isolates individual MRAM memory cells within large two-dimensional arrays of MRAM cells. An embodiment of an MRAM sense amplifier is similar to the differential amplifier of FIG. 1, and interfaces with the MRAM selection circuitry. The MRAM sense amplifier relies on sensitivity and power supply rejection. Small voltage variations of the common source node 120 can cause errors or system correction actions that affect the performance of the sense operations of the MRAM circuits. Minimizing the power supply sensitivity improves the reliability and performance of the MRAM sense circuits.
It should be noted that other types of RAM (for example, SRAM and DRAM) do not require the power supply sensitivity required by MRAM because other types of memory generally operate with much larger sense signals.
It is desirable to have a method and apparatus for minimizing power supply sensitivity of differential amplifiers. It is desirable that the method and apparatus be adaptable for use with MRAM sense amplifiers.